1. Field of the Invention
The present invention generally relates to a low power semiconductor memory device, and more specifically, to a low power semiconductor memory device which activates a sub word line driver and a bit line sense amplifier for driving a selected memory cell array block to reduce power consumption of the whole chip.
2. Description of the Prior Art
In general, when a semiconductor memory device (for example, DRAM) has a memory storage capacitance of 64 M bits, a memory array block comprises four memory blocks. In the semiconductor memory device, two memory array blocks are located up and down in a horizontal direction of a semiconductor chip. In the center there are positioned a power generating circuit and an input/output interface circuit including an address input circuit, a data input/output circuit and a bonding pad array.
As described above, two memory blocks are located left and right, and other two memory blocks are located up and down to the horizontal direction of the semiconductor chip. The two memory blocks located left and right form one group, and a main word line driver is positioned at the center. The main word line driver forms a selecting signal line of a main word line extended to penetrate one memory block. The one memory block includes a memory cell having 4 K bits in a direction of the main word line and 4 K bits in a direction of a bit line perpendicular to the main word line.
The above described one memory block is divided into 8 sub memory blocks in the direction of the main word line. A sub word line driver is located in each sub memory block. The sub word line driver is divided at a length of ⅛ to the main word line, and forms a sub word line selecting signal line extended in parallel with the main word line. In order to reduce the number of main word lines, that is, to increase line pitch of the main word line, four sub word lines are arranged in the direction of the bit line to one main word line. In this way, a sub word line driver is positioned for selecting one of the 8 sub word lines in the direction of the main word line. The sub word line driver forms a selecting signal for selecting one of the four sub word lines extended to the arrangement direction of the sub word line driver.
The 8 sub word lines are positioned in one main word line to its extension direction. The 8 sub word lines are alternately arranged in one memory cell array block. The sub word line driver located between the memory cell array blocks forms a selecting signal of the sub word line of the memory blocks located left and right.
Although the above-described memory block is divided into 8 blocks to the direction of the main word line, the sub word lines corresponding to the two memory blocks are simultaneously selected by the sub word driver. As a result, the memory block is actually divided into 4 blocks. In the above-described configuration where sub word lines are divided into the even number and the odd number and a sub word driver is located at both sides of each memory block, the actual pitch of the sub word line arranged with high density corresponding to the arrangement of the memory cell can be alleviated twice.
The sub word line driver supplies a predecoding signal in common to four sub word lines. Eight predecoding signal line for selecting one of the four sub word lines are positioned. The even numbers of the predecoding signal lines are supplied to the even number rows of the sub word line drivers. The odd numbers of the predecoding lines are supplied to the odd number rows of the sub word line drivers.
A pair of bit lines are positioned perpendicular to the sub word lines arranged in parallel with the main word lines. The bit lines are divided into the even number of rows and the odd number of rows, and bit line sense amplifiers are positioned up and down on the basis of the memory cell array block. A sense amplifier is arranged in parallel with the horizontal direction of the semiconductor chip, and a column decoder is arranged in the center of the chip.
In the configuration where the sense amplifiers are arranged at both sides of the memory block, since bit lines are allotted to the odd number of rows and the even number of rows, the pitch of the sense amplifier array can be increased. Input/output lines, which are arranged depending on the arrangement of the sense amplifiers, are connected to the bit lines through a column switch. The column switch is connected to a column selecting line for receiving a selecting signal of the column decoder.
The DRAM performs a precharge operation before the operation of the memory cell. The precharge operation is to set the bit line to a predetermined precharge voltage. In general, the precharge voltage corresponds to a half (VDD/2) of a power supply voltage VDD. The power consumption and noise which result from charge and discharge of the bit line can be reduced by setting the precharge voltage as a intermediate value between the power supply voltage VDD and the ground voltage VSS.
A word line connected to a specific memory cell is selected, and a pulse voltage (word line selecting pulse) is applied. A signal voltage resulting from information voltages VDD or VSS of a memory cell capacitor is superposed at the precharge voltage, and outputted as a positive or negative signal to the bit line.
Generally, the capacity of the cell capacitor is much smaller than parasitic capacity of the bit line, and the memory cell becomes smaller to reduce the area of the semiconductor chip. As a result, since a plurality of memory cells are connected to one bit line if possible, the cell capacitor becomes smaller and the parasitic capacity of the bit line becomes larger.
The signal voltage which is a positive or negative signal in the bit line is sensed and amplified in the sense amplifier connected to the bit line.
A bit line sense amplifier is operated with the precharge voltage (VDD/2) as a reference voltage. An output voltage of the sense amplifier becomes the power supply voltage VDD if the signal voltage is larger than the reference voltage (VDD/2), and becomes the ground voltage VSS if the signal voltage is smaller than the reference voltage (VDD/2).
Information of all memory cells on the word line for receiving a word line selecting pulse is destroyed. That is, since the capacity of the cell capacitor is sufficiently smaller than the parasitic capacity of the bit line, a storage node of the cell capacitor which has been at the level of the power supply voltage VDD or the ground voltage VSS is charged to the precharge voltage regardless of its information voltage.
As a result, the sense amplifier is positioned at all bit lines, and data are simultaneously amplified to the signal voltage VDD or VSS, and restored in each memory cell.
The operation for writing data in the selected memory cell is performed by applying a word line selecting pulse to the word line and providing one of information voltages VDD and VSS to the bit line.
Here, the read operation is performed before the write operation in order to prevent information of the unselected memory cell from being destroyed.
That is, the read operation is performed in all memory cells on the word line, and an amplification voltage corresponding to information of the memory cell is temporarily maintained in each bit line.
Thereafter, the column selecting switch is turned on to compulsorily substitute the amplification voltage of the selected bit line with the information voltage from a data bus and to input the information voltage to the selected memory cell capacitor.
Here, the amplification voltage of the unselected bit lines on the selected word line is re-written in the unselected memory cell.
The sufficient signal voltage is outputted to the bit line, and a word line selecting pulse voltage is given as one higher than the voltage obtained by adding the power supply voltage VDD and a threshold voltage of the cell transistor.
Meanwhile, the refresh operation is performed by sequentially reading all word lines. That is, the refresh operation is performed in a word line unit, and all memory cells are simultaneously refreshed on the word line. As a result, the storage node voltage of the memory cell capacitor is reduced as leakage current but restored to the initial value. Therefore, information of all memory cells are restored and memory information are maintained to the whole chip by the refresh operation performed on all word lines.
As described above, the conventional semiconductor memory device has large power consumption because whole of the sense amplifiers connected to the activated word line at an active mode are activated.